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stm32 /stm32l4+ /STM32L4S7 /RCC /CIFR

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Interpret as CIFR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (LSIRDYF)LSIRDYF 0 (LSERDYF)LSERDYF 0 (MSIRDYF)MSIRDYF 0 (HSIRDYF)HSIRDYF 0 (HSERDYF)HSERDYF 0 (PLLRDYF)PLLRDYF 0 (PLLSAI1RDYF)PLLSAI1RDYF 0 (PLLSAI2RDYF)PLLSAI2RDYF 0 (CSSF)CSSF 0 (LSECSSF)LSECSSF 0 (HSI48RDYF)HSI48RDYF

Description

Clock interrupt flag register

Fields

LSIRDYF

LSI ready interrupt flag
LSERDYF

LSE ready interrupt flag
MSIRDYF

MSI ready interrupt flag
HSIRDYF

HSI ready interrupt flag
HSERDYF

HSE ready interrupt flag
PLLRDYF

PLL ready interrupt flag
PLLSAI1RDYF

PLLSAI1 ready interrupt flag
PLLSAI2RDYF

PLLSAI2 ready interrupt flag
CSSF

Clock security system interrupt flag
LSECSSF

LSE Clock security system interrupt flag
HSI48RDYF

HSI48 ready interrupt flag

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32