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stm32 /stm32l4+ /STM32L4S9 /DSI /DSI_CMCR

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Interpret as DSI_CMCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TEARE)TEARE 0 (ARE)ARE 0 (GSW0TX)GSW0TX 0 (GSW1TX)GSW1TX 0 (GSW2TX)GSW2TX 0 (GSR0TX)GSR0TX 0 (GSR1TX)GSR1TX 0 (GSR2TX)GSR2TX 0 (GLWTX)GLWTX 0 (DSW0TX)DSW0TX 0 (DSW1TX)DSW1TX 0 (DSR0TX)DSR0TX 0 (DLWTX)DLWTX 0 (MRDPS)MRDPS

Description

DSI Host Command mode Configuration Register

Fields

TEARE

Tearing Effect Acknowledge Request Enable
ARE

Acknowledge Request Enable
GSW0TX

Generic Short Write Zero parameters Transmission
GSW1TX

Generic Short Write One parameters Transmission
GSW2TX

Generic Short Write Two parameters Transmission
GSR0TX

Generic Short Read Zero parameters Transmission
GSR1TX

Generic Short Read One parameters Transmission
GSR2TX

Generic Short Read Two parameters Transmission
GLWTX

Generic Long Write Transmission
DSW0TX

DCS Short Write Zero parameter Transmission
DSW1TX

DCS Short Read One parameter Transmission
DSR0TX

DCS Short Read Zero parameter Transmission
DLWTX

DCS Long Write Transmission
MRDPS

Maximum Read Packet Size

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32