RRSTP=B_0x0, LPMS=B_0x0, VOS=B_0x0, DBP=B_0x0
Power control register 1
| LPMS | Low-power mode selection These bits select the low-power mode entered when CPU enters the Deepsleep mode. 1xx: Shutdown mode Note: If LPR bit is set, Stop 2 mode cannot be selected and Stop 1 mode shall be entered instead of Stop 2. Note: In Standby mode, SRAM2 can be preserved or not, depending on RRS bit configuration in PWR_CR3. 0 (B_0x0): Stop 0 mode 1 (B_0x1): Stop 1 mode 2 (B_0x2): Stop 2 mode 3 (B_0x3): Standby mode |
| RRSTP | SRAM3 retention in Stop 2 mode 0 (B_0x0): SRAM3 is powered off in Stop 2 mode (SRAM3 content is lost) 1 (B_0x1): SRAM3 is powered in Stop 2 mode (RAM3 content is kept). |
| DBP | Disable backup domain write protection In reset state, the RTC and backup registers are protected against parasitic write access. This bit must be set to enable write access to these registers. 0 (B_0x0): Access to RTC and Backup registers disabled 1 (B_0x1): Access to RTC and Backup registers enabled |
| VOS | Voltage scaling range selection 0 (B_0x0): Cannot be written (forbidden by hardware) 1 (B_0x1): Range 1 2 (B_0x2): Range 2 3 (B_0x3): Cannot be written (forbidden by hardware) |
| LPR | Low-power run When this bit is set, the regulator is switched from main mode (MR) to low-power mode (LPR). Note: Stop 2 mode cannot be entered when LPR bit is set. Stop 1 is entered instead. |