IOSV=B_0x0, PVME4=B_0x0, PLS=B_0x0, PVME2=B_0x0, PVME3=B_0x0, PVME1=B_0x0, USV=B_0x0, PVDE=B_0x0
Power control register 2
| PVDE | Power voltage detector enable Note: This bit is write-protected when the bit PVDL (PVD Lock) is set in the SYSCFG_CBR register. Note: This bit is reset only by a system reset. 0 (B_0x0): Power voltage detector disable. 1 (B_0x1): Power voltage detector enable. |
| PLS | Power voltage detector level selection. These bits select the voltage threshold detected by the power voltage detector: Note: These bits are write-protected when the bit PVDL (PVD Lock) is set in the SYSCFG_CBR register. Note: These bits are reset only by a system reset. 0 (B_0x0): VPVD0 around 2.0 V 1 (B_0x1): VPVD1 around 2.2 V 2 (B_0x2): VPVD2 around 2.4 V 3 (B_0x3): VPVD3 around 2.5 V 4 (B_0x4): VPVD4 around 2.6 V 5 (B_0x5): VPVD5 around 2.8 V 6 (B_0x6): VPVD6 around 2.9 V 7 (B_0x7): External input analog voltage PVD_IN (compared internally to VREFINT) |
| PVME1 | Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2V 0 (B_0x0): PVM1 (VDDUSB monitoring vs. 1.2V threshold) disable. 1 (B_0x1): PVM1 (VDDUSB monitoring vs. 1.2V threshold) enable. |
| PVME2 | Peripheral voltage monitoring 2 enable: VDDIO2 vs. 0.9V 0 (B_0x0): PVM2 (VDDIO2 monitoring vs. 0.9V threshold) disable. 1 (B_0x1): PVM2 (VDDIO2 monitoring vs. 0.9V threshold) enable. |
| PVME3 | Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V 0 (B_0x0): PVM3 (VDDA monitoring vs. 1.62V threshold) disable. 1 (B_0x1): PVM3 (VDDA monitoring vs. 1.62V threshold) enable. |
| PVME4 | Peripheral voltage monitoring 4 enable: VDDA vs. 2.2V 0 (B_0x0): PVM4 (VDDA monitoring vs. 2.2V threshold) disable. 1 (B_0x1): PVM4 (VDDA monitoring vs. 2.2V threshold) enable. |
| IOSV | VDDIO2 Independent I/Os supply valid This bit is used to validate the VDDIO2 supply for electrical and logical isolation purpose. Setting this bit is mandatory to use PG[15:2]. If VDDIO2 is not always present in the application, the PVM can be used to determine whether this supply is ready or not. 0 (B_0x0): VDDIO2 is not present. Logical and electrical isolation is applied to ignore this supply. 1 (B_0x1): VDDIO2 is valid. |
| USV | VDDUSB USB supply valid This bit is used to validate the VDDUSB supply for electrical and logical isolation purpose. Setting this bit is mandatory to use the USB OTG_FS peripheral. If VDDUSB is not always present in the application, the PVM can be used to determine whether this supply is ready or not. 0 (B_0x0): VDDUSB is not present. Logical and electrical isolation is applied to ignore this supply. 1 (B_0x1): VDDUSB is valid. |