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stm32 /stm32l4 /STM32L496 /ADC1 /DIFSEL

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Interpret as DIFSEL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DIFSEL_0)DIFSEL_0 0DIFSEL_1_150DIFSEL_16_18

Description

Differential Mode Selection Register 2

Fields

DIFSEL_0

Differential mode for channels 0
DIFSEL_1_15

Differential mode for channels 15 to 1
DIFSEL_16_18

Differential mode for channels 18 to 16

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32