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stm32 /stm32l4 /STM32L496 /DBGMCU /APB1_FZR2

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Interpret as APB1_FZR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DBG_LPTIM2_STOP)DBG_LPTIM2_STOP

Description

APB Low Freeze Register 2

Fields

DBG_LPTIM2_STOP

LPTIM2 counter stopped when core is halted

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32