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stm32 /stm32l4 /STM32L496 /LCD /LCD_CLR

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Interpret as LCD_CLR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)SOFC 0 (B_0x0)UDDC

SOFC=B_0x0, UDDC=B_0x0

Description

LCD clear register

Fields

SOFC

Start of frame flag clear This bit is written by software to clear the SOF flag in the LCD_SR register.

0 (B_0x0): No effect

1 (B_0x1): Clear SOF flag.
UDDC

Update display done clear This bit is written by software to clear the UDD flag in the LCD_SR register.

0 (B_0x0): No effect

1 (B_0x1): Clear UDD flag.

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32