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stm32 /stm32l4 /STM32L496 /RCC /AHB1ENR

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Interpret as AHB1ENR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DMA1EN)DMA1EN 0 (DMA2EN)DMA2EN 0 (FLASHEN)FLASHEN 0 (CRCEN)CRCEN 0 (TSCEN)TSCEN 0 (DMA2DEN)DMA2DEN

Description

AHB1 peripheral clock enable register

Fields

DMA1EN

DMA1 clock enable
DMA2EN

DMA2 clock enable
FLASHEN

Flash memory interface clock enable
CRCEN

CRC clock enable
TSCEN

Touch Sensing Controller clock enable
DMA2DEN

DMA2D clock enable

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32