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stm32 /stm32l4 /STM32L496 /RCC /APB2SMENR

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Interpret as APB2SMENR

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https://regviz.com/r/stm32/stm32l4/STM32L476/RCC/APB2SMENR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SYSCFGSMEN)SYSCFGSMEN 0 (SDMMCSMEN)SDMMCSMEN 0 (TIM1SMEN)TIM1SMEN 0 (SPI1SMEN)SPI1SMEN 0 (TIM8SMEN)TIM8SMEN 0 (USART1SMEN)USART1SMEN 0 (TIM15SMEN)TIM15SMEN 0 (TIM16SMEN)TIM16SMEN 0 (TIM17SMEN)TIM17SMEN 0 (SAI1SMEN)SAI1SMEN 0 (SAI2SMEN)SAI2SMEN 0 (DFSDMSMEN)DFSDMSMEN

Description

APB2SMENR

Fields

SYSCFGSMEN

SYSCFG clocks enable during Sleep and Stop modes
SDMMCSMEN

SDMMC clocks enable during Sleep and Stop modes
TIM1SMEN

TIM1 timer clocks enable during Sleep and Stop modes
SPI1SMEN

SPI1 clocks enable during Sleep and Stop modes
TIM8SMEN

TIM8 timer clocks enable during Sleep and Stop modes
USART1SMEN

USART1clocks enable during Sleep and Stop modes
TIM15SMEN

TIM15 timer clocks enable during Sleep and Stop modes
TIM16SMEN

TIM16 timer clocks enable during Sleep and Stop modes
TIM17SMEN

TIM17 timer clocks enable during Sleep and Stop modes
SAI1SMEN

SAI1 clocks enable during Sleep and Stop modes
SAI2SMEN

SAI2 clocks enable during Sleep and Stop modes
DFSDMSMEN

DFSDM timer clocks enable during Sleep and Stop modes

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32