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stm32 /stm32l4 /STM32L496 /TIM1 /OR1

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Interpret as OR1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0ETR_ADC1_RMP 0ETR_ADC3_RMP 0 (TI1_RMP)TI1_RMP

Description

DMA address for full transfer

Fields

ETR_ADC1_RMP

External trigger remap on ADC1 analog watchdog
ETR_ADC3_RMP

External trigger remap on ADC3 analog watchdog
TI1_RMP

Input Capture 1 remap

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32