stm32 /stm32l4 /STM32L4x2 /ADC1 /ADC_CFGR

Direct memory access enable This bit is set and cleared by software to enable the generation of DMA requests. This allows to use the DMA to manage automatically the converted data. For more details, refer to Section : Managing conversions using the DMA. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: In dual-ADC modes, this bit is not relevant and replaced by control bits MDMA[1:0] of the ADCx_CCR register.

0 (B_0x0): DMA disabled

1 (B_0x1): DMA enabled

Direct memory access configuration This bit is set and cleared by software to select between two DMA modes of operation and is effective only when DMAEN = 1. For more details, refer to Section : Managing conversions using the DMA Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: In dual-ADC modes, this bit is not relevant and replaced by control bit DMACFG of the ADCx_CCR register.

0 (B_0x0): DMA One Shot mode selected

1 (B_0x1): DMA Circular mode selected

DFSDM mode configuration This bit is set and cleared by software to enable the DFSDM mode. It is effective only when DMAEN = 0. Note: To make sure no conversion is ongoing, the software is allowed to write this bit only when ADSTART= 0 and JADSTART= 0.

0 (B_0x0): DFSDM mode disabled

1 (B_0x1): DFSDM mode enabled

Data resolution These bits are written by software to select the resolution of the conversion. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).

0 (B_0x0): 12-bit

1 (B_0x1): 10-bit

2 (B_0x2): 8-bit

3 (B_0x3): 6-bit

Data alignment This bit is set and cleared by software to select right or left alignment. Refer to Section : Data register, data alignment and offset (ADC_DR, OFFSETy, OFFSETy_CH, ALIGN) Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).

0 (B_0x0): Right alignment

1 (B_0x1): Left alignment

External trigger selection for regular group These bits select the external event used to trigger the start of conversion of a regular group: … Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).

0 (B_0x0): Event 0

1 (B_0x1): Event 1

External trigger selection for regular group These bits select the external event used to trigger the start of conversion of a regular group: … Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).

0 (B_0x0): Event 0

1 (B_0x1): Event 1

External trigger selection for regular group These bits select the external event used to trigger the start of conversion of a regular group: … Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).

0 (B_0x0): Event 0

1 (B_0x1): Event 1

External trigger selection for regular group These bits select the external event used to trigger the start of conversion of a regular group: … Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).

0 (B_0x0): Event 0

1 (B_0x1): Event 1

External trigger enable and polarity selection for regular channels These bits are set and cleared by software to select the external trigger polarity and enable the trigger of a regular group. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).

0 (B_0x0): Hardware trigger detection disabled (conversions can be launched by software)

1 (B_0x1): Hardware trigger detection on the rising edge

2 (B_0x2): Hardware trigger detection on the falling edge

3 (B_0x3): Hardware trigger detection on both the rising and falling edges

Overrun mode This bit is set and cleared by software and configure the way data overrun is managed. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing).

0 (B_0x0): ADC_DR register is preserved with the old data when an overrun is detected.

1 (B_0x1): ADC_DR register is overwritten with the last conversion result when an overrun is detected.

Single / continuous conversion mode for regular conversions This bit is set and cleared by software. If it is set, regular conversion takes place continuously until it is cleared. Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both DISCEN = 1 and CONT = 1. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing). Note: When dual mode is enabled (DUAL bits in ADCx_CCR register are not equal to zero), the bit CONT of the slave ADC is no more writable and its content is equal to the bit CONT of the master ADC.

0 (B_0x0): Single conversion mode

1 (B_0x1): Continuous conversion mode

Delayed conversion mode This bit is set and cleared by software to enable/disable the Auto Delayed Conversion mode. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Note: When dual mode is enabled (DUAL bits in ADCx_CCR register are not equal to zero), the bit AUTDLY of the slave ADC is no more writable and its content is equal to the bit AUTDLY of the master ADC.

0 (B_0x0): Auto-delayed conversion mode off

1 (B_0x1): Auto-delayed conversion mode on

Discontinuous mode for regular channels This bit is set and cleared by software to enable/disable Discontinuous mode for regular channels. Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both DISCEN = 1 and CONT = 1. Note: It is not possible to use both auto-injected mode and discontinuous mode simultaneously: the bits DISCEN and JDISCEN must be kept cleared by software when JAUTO is set. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing). Note: When dual mode is enabled (DUAL bits in ADCx_CCR register are not equal to zero), the bit DISCEN of the slave ADC is no more writable and its content is equal to the bit DISCEN of the master ADC.

0 (B_0x0): Discontinuous mode for regular channels disabled

1 (B_0x1): Discontinuous mode for regular channels enabled

Discontinuous mode channel count These bits are written by software to define the number of regular channels to be converted in discontinuous mode, after receiving an external trigger. … Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). Note: When dual mode is enabled (DUAL bits in ADCx_CCR register are not equal to zero), the bits DISCNUM[2:0] of the slave ADC are no more writable and their content is equal to the bits DISCNUM[2:0] of the master ADC.

0 (B_0x0): 1 channel

1 (B_0x1): 2 channels

7 (B_0x7): 8 channels

Discontinuous mode on injected channels This bit is set and cleared by software to enable/disable discontinuous mode on the injected channels of a group. Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing). Note: It is not possible to use both auto-injected mode and discontinuous mode simultaneously: the bits DISCEN and JDISCEN must be kept cleared by software when JAUTO is set. Note: When dual mode is enabled (bits DUAL of ADCx_CCR register are not equal to zero), the bit JDISCEN of the slave ADC is no more writable and its content is equal to the bit JDISCEN of the master ADC.

0 (B_0x0): Discontinuous mode on injected channels disabled

1 (B_0x1): Discontinuous mode on injected channels enabled

JSQR queue mode This bit is set and cleared by software. It defines how an empty Queue is managed. Refer to Section 16.4.21: Queue of context for injected conversions for more information. Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing). Note: When dual mode is enabled (DUAL bits in ADCx_CCR register are not equal to zero), the bit JQM of the slave ADC is no more writable and its content is equal to the bit JQM of the master ADC.

0 (B_0x0): JSQR mode 0: The Queue is never empty and maintains the last written configuration into JSQR.

1 (B_0x1): JSQR mode 1: The Queue can be empty and when this occurs, the software and hardware triggers of the injected sequence are both internally disabled just after the completion of the last valid injected sequence.

Enable the watchdog 1 on a single channel or on all channels This bit is set and cleared by software to enable the analog watchdog on the channel identified by the AWD1CH[4:0] bits or on all the channels Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).

0 (B_0x0): Analog watchdog 1 enabled on all channels

1 (B_0x1): Analog watchdog 1 enabled on a single channel

Analog watchdog 1 enable on regular channels This bit is set and cleared by software Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing).

0 (B_0x0): Analog watchdog 1 disabled on regular channels

1 (B_0x1): Analog watchdog 1 enabled on regular channels

Analog watchdog 1 enable on injected channels This bit is set and cleared by software Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing).

0 (B_0x0): Analog watchdog 1 disabled on injected channels

1 (B_0x1): Analog watchdog 1 enabled on injected channels

Automatic injected group conversion This bit is set and cleared by software to enable/disable automatic injected group conversion after regular group conversion. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no regular nor injected conversion is ongoing). Note: When dual mode is enabled (DUAL bits in ADCx_CCR register are not equal to zero), the bit JAUTO of the slave ADC is no more writable and its content is equal to the bit JAUTO of the master ADC.

0 (B_0x0): Automatic injected group conversion disabled

1 (B_0x1): Automatic injected group conversion enabled

Analog watchdog 1 channel selection These bits are set and cleared by software. They select the input channel to be guarded by the analog watchdog. … others: reserved, must not be used Note: Some channels are not connected physically. Keep the corresponding AWD1CH[4:0] setting to the reset value. Note: The channel selected by AWD1CH must be also selected into the SQRi or JSQRi registers. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).

0 (B_0x0): ADC analog input channel 0 monitored by AWD1 (available on ADC1 only)

1 (B_0x1): ADC analog input channel 1 monitored by AWD1

18 (B_0x12): ADC analog input channel 18 monitored by AWD1

Injected Queue disable These bits are set and cleared by software to disable the Injected Queue mechanism : Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no regular nor injected conversion is ongoing). Note: A set or reset of JQDIS bit causes the injected queue to be flushed and the JSQR register is cleared.

0 (B_0x0): Injected Queue enabled

1 (B_0x1): Injected Queue disabled