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stm32 /stm32l4 /STM32L4x2 /ADC1 /ADC_DIFSEL

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Interpret as ADC_DIFSEL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DIFSEL

Description

ADC differential mode selection register

Fields

DIFSEL

Differential mode for channels 18 to 0. These bits are set and cleared by software. They allow to select if a channel is configured as single-ended or differential mode. DIFSEL[i] = 0: ADC analog input channel is configured in single ended mode DIFSEL[i] = 1: ADC analog input channel i is configured in differential mode Note: The DIFSEL bits corresponding to channels that are either connected to a single-ended I/O port or to an internal channel must be kept their reset value (single-ended input mode). Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL = 0, JADSTART = 0, JADSTP = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32