stm32 /stm32l4 /STM32L4x2 /ADC123_Common /ADC_CCR

Dual ADC mode selection These bits are written by software to select the operating mode. All the ADCs independent: 00001 to 01001: Dual mode, master and slave ADCs working together All other combinations are reserved and must not be programmed Note: The software is allowed to write these bits only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).

0 (B_0x0): Independent mode

1 (B_0x1): Combined regular simultaneous + injected simultaneous mode

2 (B_0x2): Combined regular simultaneous + alternate trigger mode

3 (B_0x3): Combined Interleaved mode + injected simultaneous mode

5 (B_0x5): Injected simultaneous mode only

6 (B_0x6): Regular simultaneous mode only

7 (B_0x7): Interleaved mode only

9 (B_0x9): Alternate trigger mode only

Delay between 2 sampling phases These bits are set and cleared by software. These bits are used in dual interleaved modes. Refer to Table 112 for the value of ADC resolution versus DELAY bits values. Note: The software is allowed to write these bits only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).

DMA configuration (for dual ADC mode) This bit is set and cleared by software to select between two DMA modes of operation and is effective only when DMAEN = 1. For more details, refer to Section : Managing conversions using the DMA Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).

0 (B_0x0): DMA One Shot mode selected

1 (B_0x1): DMA Circular mode selected

Direct memory access mode for dual ADC mode This bitfield is set and cleared by software. Refer to the DMA controller section for more details. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).

0 (B_0x0): MDMA mode disabled

1 (B_0x1): Enable dual interleaved mode to output to the master channel of DFSDM interface both Master and the Slave result (16-bit data width)

2 (B_0x2): MDMA mode enabled for 12 and 10-bit resolution

3 (B_0x3): MDMA mode enabled for 8 and 6-bit resolution

ADC clock mode These bits are set and cleared by software to define the ADC clock scheme (which is common to both master and slave ADCs): In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a conversion. Note: The software is allowed to write these bits only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).

0 (B_0x0): CK_ADCx (x = 123) (Asynchronous clock mode), generated at product level (refer to Section 6: Reset and clock control (RCC))

1 (B_0x1): HCLK/1 (Synchronous clock mode). This configuration must be enabled only if the AHB clock prescaler is set (HPRE[3:0] = 0xxx in RCC_CFGR register) and if the system clock has a 50% duty cycle.

2 (B_0x2): HCLK/2 (Synchronous clock mode)

3 (B_0x3): HCLK/4 (Synchronous clock mode)

ADC prescaler These bits are set and cleared by software to select the frequency of the clock to the ADC. The clock is common for all the ADCs. other: reserved Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). The ADC prescaler value is applied only when CKMODE[1:0] = 00.

0 (B_0x0): input ADC clock not divided

1 (B_0x1): input ADC clock divided by 2

2 (B_0x2): input ADC clock divided by 4

3 (B_0x3): input ADC clock divided by 6

4 (B_0x4): input ADC clock divided by 8

5 (B_0x5): input ADC clock divided by 10

6 (B_0x6): input ADC clock divided by 12

7 (B_0x7): input ADC clock divided by 16

8 (B_0x8): input ADC clock divided by 32

9 (B_0x9): input ADC clock divided by 64

10 (B_0xA): input ADC clock divided by 128

11 (B_0xB): input ADC clock divided by 256

V_REFINT enable This bit is set and cleared by software to enable/disable the V_REFINT channel.

0 (B_0x0): V_REFINT channel disabled

1 (B_0x1): V_REFINT channel enabled

CH17 selection This bit is set and cleared by software to control channel 17.

0 (B_0x0): Temperature sensor channel disabled, dac_out1 selected

1 (B_0x1): Temperature sensor channel enabled

CH18 selection This bit is set and cleared by software to control channel 18.

0 (B_0x0): V_BAT channel disabled, dac_out2 selected.

1 (B_0x1): V_BAT channel enabled