Regviz

stm32 /stm32l4 /STM32L4x6 /TIM8 /OR1

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as OR1

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32l4/STM32L4x5/TIM8/OR1#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0ETR_ADC2_RMP 0ETR_ADC3_RMP 0 (TI1_RMP)TI1_RMP

Description

DMA address for full transfer

Fields

ETR_ADC2_RMP

External trigger remap on ADC2 analog watchdog
ETR_ADC3_RMP

External trigger remap on ADC3 analog watchdog
TI1_RMP

Input Capture 1 remap

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32