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stm32 /stm32l5 /STM32L562 /DAC /DAC_SHHR

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Interpret as DAC_SHHR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0THOLD10THOLD2

Description

DAC Sample and Hold hold time register

Fields

THOLD1

DAC Channel 1 hold Time (only valid in sample & hold mode) Hold time= (THOLD[9:0]) x T LSI
THOLD2

DAC Channel 2 hold time (only valid in sample & hold mode). Hold time= (THOLD[9:0]) x T LSI

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32