Regviz

stm32 /stm32l5 /STM32L562 /DBGMCU /APB1LFZR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as APB1LFZR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32l5/STM32L552/DBGMCU/APB1LFZR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DBG_TIM2_STOP)DBG_TIM2_STOP 0 (DBG_TIM3_STOP)DBG_TIM3_STOP 0 (DBG_TIM4_STOP)DBG_TIM4_STOP 0 (DBG_TIM5_STOP)DBG_TIM5_STOP 0 (DBG_TIM6_STOP)DBG_TIM6_STOP 0 (DBG_TIM7_STOP)DBG_TIM7_STOP 0 (DBG_RTC_STOP)DBG_RTC_STOP 0 (DBG_WWDG_STOP)DBG_WWDG_STOP 0 (DBG_IWDG_STOP)DBG_IWDG_STOP 0 (DBG_I2C1_STOP)DBG_I2C1_STOP 0 (DBG_I2C2_STOP)DBG_I2C2_STOP 0 (DBG_I2C3_STOP)DBG_I2C3_STOP 0 (DBG_LPTIM1_STOP)DBG_LPTIM1_STOP

Description

Debug MCU APB1 freeze register1

Fields

DBG_TIM2_STOP

TIM2 counter stopped when core is halted
DBG_TIM3_STOP

TIM3 stop in debug
DBG_TIM4_STOP

TIM4 stop in debug
DBG_TIM5_STOP

TIM5 stop in debug
DBG_TIM6_STOP

TIM6 counter stopped when core is halted
DBG_TIM7_STOP

TIM7 counter stopped when core is halted
DBG_RTC_STOP

RTC counter stopped when core is halted
DBG_WWDG_STOP

Window watchdog counter stopped when core is halted
DBG_IWDG_STOP

Independent watchdog counter stopped when core is halted
DBG_I2C1_STOP

I2C1 SMBUS timeout counter stopped when core is halted
DBG_I2C2_STOP

I2C2 SMBUS timeout counter stopped when core is halted
DBG_I2C3_STOP

I2C3 SMBUS timeout counter stopped when core is halted
DBG_LPTIM1_STOP

LPTIM1 counter stopped when core is halted

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32