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stm32 /stm32l5 /STM32L562 /GPIOA /SECCFGR

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Interpret as SECCFGR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SEC0)SEC0 0 (SEC1)SEC1 0 (SEC2)SEC2 0 (SEC3)SEC3 0 (SEC4)SEC4 0 (SEC5)SEC5 0 (SEC6)SEC6 0 (SEC7)SEC7 0 (SEC8)SEC8 0 (SEC9)SEC9 0 (SEC10)SEC10 0 (SEC11)SEC11 0 (SEC12)SEC12 0 (SEC13)SEC13 0 (SEC14)SEC14 0 (SEC15)SEC15

Description

GPIO secure configuration register

Fields

SEC0

I/O pin of Port x secure bit enable
SEC1

I/O pin of Port x secure bit enable
SEC2

I/O pin of Port x secure bit enable
SEC3

I/O pin of Port x secure bit enable
SEC4

I/O pin of Port x secure bit enable
SEC5

I/O pin of Port x secure bit enable
SEC6

I/O pin of Port x secure bit enable
SEC7

I/O pin of Port x secure bit enable
SEC8

I/O pin of Port x secure bit enable
SEC9

I/O pin of Port x secure bit enable
SEC10

I/O pin of Port x secure bit enable
SEC11

I/O pin of Port x secure bit enable
SEC12

I/O pin of Port x secure bit enable
SEC13

I/O pin of Port x secure bit enable
SEC14

I/O pin of Port x secure bit enable
SEC15

I/O pin of Port x secure bit enable

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32