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stm32 /stm32l5 /STM32L562 /GTZC_TZIC /IER3

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Interpret as IER3

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TZSCIE)TZSCIE 0 (TZICIE)TZICIE 0 (MPCWM1IE)MPCWM1IE 0 (MPCWM2IE)MPCWM2IE 0 (MPCBB1IE)MPCBB1IE 0 (MPCBB1_REGIE)MPCBB1_REGIE 0 (MPCBB2IE)MPCBB2IE 0 (MPCBB2_REGIE)MPCBB2_REGIE

Description

TZIC interrupt enable register 3

Fields

TZSCIE

TZSCIE
TZICIE

TZICIE
MPCWM1IE

MPCWM1IE
MPCWM2IE

MPCWM2IE
MPCBB1IE

MPCBB1IE
MPCBB1_REGIE

MPCBB1_REGIE
MPCBB2IE

MPCBB2IE
MPCBB2_REGIE

MPCBB2_REGIE

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32