Regviz

stm32 /stm32l5 /STM32L562 /OCTOSPI1 /WCCR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as WCCR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32l5/STM32L552/OCTOSPI1/WCCR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0IMODE0 (IDTR)IDTR 0ISIZE 0ADMODE 0 (ADDTR)ADDTR 0ADSIZE 0ABMODE 0 (ABDTR)ABDTR 0ABSIZE 0DMODE0 (DDTR)DDTR 0 (DQSE)DQSE

Description

WCCR

Fields

IMODE

IMODE
IDTR

IDTR
ISIZE

ISIZE
ADMODE

ADMODE
ADDTR

ADDTR
ADSIZE

ADSIZE
ABMODE

ABMODE
ABDTR

ABDTR
ABSIZE

ABSIZE
DMODE

DMODE
DDTR

DDTR
DQSE

DQSE

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32