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stm32 /stm32l5 /STM32L562 /TAMP /MISR

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Interpret as MISR

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https://regviz.com/r/stm32/stm32l5/STM32L552/TAMP/MISR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TAMP1MF)TAMP1MF 0 (TAMP2MF)TAMP2MF 0 (TAMP3MF)TAMP3MF 0 (TAMP4MF)TAMP4MF 0 (TAMP5MF)TAMP5MF 0 (TAMP6MF)TAMP6MF 0 (TAMP7MF)TAMP7MF 0 (TAMP8MF)TAMP8MF 0 (ITAMP1MF)ITAMP1MF 0 (ITAMP2MF)ITAMP2MF 0 (ITAMP3MF)ITAMP3MF 0 (ITAMP5MF)ITAMP5MF 0 (ITAMP8MF)ITAMP8MF

Description

TAMP masked interrupt status register

Fields

TAMP1MF

TAMP1MF:
TAMP2MF

TAMP2MF
TAMP3MF

TAMP3MF
TAMP4MF

TAMP4MF
TAMP5MF

TAMP5MF
TAMP6MF

TAMP6MF
TAMP7MF

TAMP7MF:
TAMP8MF

TAMP8MF
ITAMP1MF

ITAMP1MF
ITAMP2MF

ITAMP2MF
ITAMP3MF

ITAMP3MF
ITAMP5MF

ITAMP5MF
ITAMP8MF

ITAMP8MF

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32