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stm32 /stm32l5 /STM32L562 /TIM15 /OR2

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Interpret as OR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (BKINE)BKINE 0 (BKCMP1E)BKCMP1E 0 (BKCMP2E)BKCMP2E 0 (BKDF1BK0E)BKDF1BK0E 0 (BKINP)BKINP 0 (BKCMP1P)BKCMP1P 0 (BKCMP2P)BKCMP2P

Description

TIM15 option register 2

Fields

BKINE

BRK BKIN input enable
BKCMP1E

BRK COMP1 enable
BKCMP2E

BRK COMP2 enable
BKDF1BK0E

BRK dfsdm1_break[0] enable
BKINP

BRK BKIN input polarity
BKCMP1P

BRK COMP1 input polarity
BKCMP2P

BRK COMP2 input polarity

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32