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stm32 /stm32l5 /STM32L562 /TIM2 /OR1

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Interpret as OR1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ITR1_RMP)ITR1_RMP 0 (ETR1_RMP)ETR1_RMP 0TI4_RMP

Description

TIM2 option register

Fields

ITR1_RMP

Internal trigger 1 remap
ETR1_RMP

External trigger remap
TI4_RMP

Input Capture 4 remap

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32