CONT=B_0x0, OVRMOD=B_0x0, JQM=B_0x0, AWD1CH=B_0x0, JAUTO=B_0x0, DISCEN=B_0x0, AUTDLY=B_0x0, EXTEN=B_0x0, EXTSEL=B_0x0, RES=B_0x0, JDISCEN=B_0x0, DMNGT=B_0x0, AWD1EN=B_0x0, JQDIS=B_0x0, JAWD1EN=B_0x0, AWD1SGL=B_0x0, DISCNUM=B_0x0
ADC configuration register
| DMNGT | Data management configuration 0 (B_0x0): Regular conversion data stored in DR only 1 (B_0x1): DMA One-shot mode selected 2 (B_0x2): MDF mode detected 3 (B_0x3): DMA Circular mode selected |
| RES | Data resolution 0 (B_0x0): 12-bit 1 (B_0x1): 10-bit 2 (B_0x2): 8-bit 3 (B_0x3): 6-bit |
| EXTSEL | External trigger selection for regular group 0 (B_0x0): adc_ext_trg0 1 (B_0x1): adc_ext_trg1 2 (B_0x2): adc_ext_trg2 3 (B_0x3): adc_ext_trg3 4 (B_0x4): adc_ext_trg4 5 (B_0x5): adc_ext_trg5 6 (B_0x6): adc_ext_trg6 7 (B_0x7): adc_ext_trg7 31 (B_0x1F): adc_ext_trg31 |
| EXTEN | External trigger enable and polarity selection for regular channels 0 (B_0x0): Hardware trigger detection disabled (conversions can be launched by software) 1 (B_0x1): Hardware trigger detection on the rising edge 2 (B_0x2): Hardware trigger detection on the falling edge 3 (B_0x3): Hardware trigger detection on both the rising and falling edges |
| OVRMOD | Overrun mode 0 (B_0x0): ADC_DR register is preserved with the old data when an overrun is detected. 1 (B_0x1): ADC_DR register is overwritten with the last conversion result when an overrun is detected. |
| CONT | Single / Continuous conversion mode for regular conversions 0 (B_0x0): Single conversion mode 1 (B_0x1): Continuous conversion mode |
| AUTDLY | Delayed conversion mode 0 (B_0x0): Auto-delayed conversion mode off 1 (B_0x1): Auto-delayed conversion mode on |
| DISCEN | Discontinuous mode for regular channels 0 (B_0x0): Discontinuous mode for regular channels disabled 1 (B_0x1): Discontinuous mode for regular channels enabled |
| DISCNUM | Discontinuous mode channel count 0 (B_0x0): 1 channel 1 (B_0x1): 2 channels 7 (B_0x7): 8 channels |
| JDISCEN | Discontinuous mode on injected channels 0 (B_0x0): Discontinuous mode on injected channels disabled 1 (B_0x1): Discontinuous mode on injected channels enabled |
| JQM | JSQR queue mode 0 (B_0x0): JSQR mode 0: The Queue is never empty and maintains the last written configuration into JSQR. 1 (B_0x1): JSQR mode 1: The Queue can be empty and when this occurs, the software and hardware triggers of the injected sequence are both internally disabled just after the completion of the last valid injected sequence. |
| AWD1SGL | Enable the watchdog 1 on a single channel or on all channels 0 (B_0x0): Analog watchdog 1 enabled on all channels 1 (B_0x1): Analog watchdog 1 enabled on a single channel |
| AWD1EN | Analog watchdog 1 enable on regular channels 0 (B_0x0): Analog watchdog 1 disabled on regular channels 1 (B_0x1): Analog watchdog 1 enabled on regular channels |
| JAWD1EN | Analog watchdog 1 enable on injected channels 0 (B_0x0): Analog watchdog 1 disabled on injected channels 1 (B_0x1): Analog watchdog 1 enabled on injected channels |
| JAUTO | Automatic injected group conversion 0 (B_0x0): Automatic injected group conversion disabled 1 (B_0x1): Automatic injected group conversion enabled |
| AWD1CH | Analog watchdog 1 channel selection 0 (B_0x0): ADC analog input channel 0 monitored by AWD1 1 (B_0x1): ADC analog input channel 1 monitored by AWD1 19 (B_0x13): ADC analog input channel 19 monitored by AWD1 |
| JQDIS | Injected queue disable 0 (B_0x0): Injected queue enabled 1 (B_0x1): Injected queue disabled |