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stm32 /stm32n6 /STM32N645 /DCMI /DCMI_SR

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Interpret as DCMI_SR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)HSYNC 0 (B_0x0)VSYNC 0 (B_0x0)FNE

VSYNC=B_0x0, HSYNC=B_0x0, FNE=B_0x0

Description

DCMI status register

Fields

HSYNC

Horizontal synchronization

0 (B_0x0): active line

1 (B_0x1): synchronization between lines
VSYNC

Vertical synchronization

0 (B_0x0): active frame

1 (B_0x1): synchronization between frames
FNE

FIFO not empty

0 (B_0x0): FIFO empty

1 (B_0x1): FIFO contains valid data.

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32