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stm32 /stm32n6 /STM32N645 /I3C1 /I3C_SR

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Interpret as I3C_SR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0XDCNT0 (B_0x0)ABT 0 (B_0x0)DIR 0MID

ABT=B_0x0, DIR=B_0x0

Description

I3C status register

Fields

XDCNT

Data counter
ABT

A private read message is ended prematurely by the target (when the I3C acts as controller)

0 (B_0x0): no early completion from the target

1 (B_0x1): early completion from the target
DIR

Message direction

0 (B_0x0): write

1 (B_0x1): read
MID

Message identifier/counter of a given frame (when the I3C acts as controller)

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32