FIDX=B_0x0, IDIR=B_0x0, IBLK=B_0x0, IE=B_0x0, IPOS=B_0x0
TIM2 timer encoder control register
| IE | Index enable 0 (B_0x0): Index disabled 1 (B_0x1): Index enabled |
| IDIR | Index direction 0 (B_0x0): Index resets the counter whatever the direction 1 (B_0x1): Index resets the counter when up-counting only 2 (B_0x2): Index resets the counter when down-counting only |
| IBLK | Index blanking 0 (B_0x0): Index always active 1 (B_0x1): Index disabled hen tim_ti3 input is active, as per CC3P bitfield 2 (B_0x2): Index disabled when tim_ti4 input is active, as per CC4P bitfield |
| FIDX | First index 0 (B_0x0): Index is always active 1 (B_0x1): the first Index only resets the counter |
| IPOS | Index positioning 0 (B_0x0): Index resets the counter when AB = 00 1 (B_0x1): Index resets the counter when AB = 01 2 (B_0x2): Index resets the counter when AB = 10 3 (B_0x3): Index resets the counter when AB = 11 |
| PW | Pulse width |
| PWPRSC | Pulse width prescaler |