JL=B_0x0, JEXTSEL=B_0x0, JEXTEN=B_0x0
ADC injected sequence register
| JL | Injected channel sequence length 0 (B_0x0): 1 conversion 1 (B_0x1): 2 conversions 2 (B_0x2): 3 conversions 3 (B_0x3): 4 conversions |
| JEXTSEL | External trigger selection for injected group 0 (B_0x0): adc_jext_trg0 1 (B_0x1): adc_jext_trg1 2 (B_0x2): adc_jext_trg2 3 (B_0x3): adc_jext_trg3 4 (B_0x4): adc_jext_trg4 5 (B_0x5): adc_jext_trg5 6 (B_0x6): adc_jext_trg6 7 (B_0x7): adc_jext_trg7 31 (B_0x1F): adc_jext_trg31 |
| JEXTEN | External trigger enable and polarity selection for injected channels 0 (B_0x0): Hardware trigger detection disabled (conversions can be launched by software) 1 (B_0x1): Hardware trigger detection on the rising edge 2 (B_0x2): Hardware trigger detection on the falling edge 3 (B_0x3): Hardware trigger detection on both the rising and falling edges |
| JSQ1 | 1st conversion in the injected sequence |
| JSQ2 | 2nd conversion in the injected sequence |
| JSQ3 | 3rd conversion in the injected sequence |
| JSQ4 | 4th conversion in the injected sequence |