Regviz

stm32 /stm32n6 /STM32N647 /DBGMCU /DBGMCU_APB1LFZ1

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as DBGMCU_APB1LFZ1

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32n6/STM32N645/DBGMCU/DBGMCU_APB1LFZ1#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)DBG_TIM2_STOP 0 (B_0x0)DBG_TIM3_STOP 0 (B_0x0)DBG_TIM4_STOP 0 (B_0x0)DBG_TIM5_STOP 0 (B_0x0)DBG_TIM6_STOP 0 (B_0x0)DBG_TIM7_STOP 0 (B_0x0)DBG_TIM12_STOP 0 (B_0x0)DBG_TIM13_STOP 0 (B_0x0)DBG_TIM14_STOP 0 (B_0x0)DBG_LPTIM1_STOP 0 (B_0x0)DBG_WWDG1_STOP 0 (B_0x0)DBG_TIM10_STOP 0 (B_0x0)DBG_TIM11_STOP 0 (B_0x0)DBG_I2C1_STOP 0 (B_0x0)DBG_I2C2_STOP 0 (B_0x0)DBG_I2C3_STOP 0 (B_0x0)DBG_I3C1_STOP 0 (B_0x0)DBG_I3C2_STOP

DBG_I3C2_STOP=B_0x0, DBG_I2C3_STOP=B_0x0, DBG_TIM12_STOP=B_0x0, DBG_TIM14_STOP=B_0x0, DBG_WWDG1_STOP=B_0x0, DBG_TIM5_STOP=B_0x0, DBG_TIM13_STOP=B_0x0, DBG_TIM3_STOP=B_0x0, DBG_TIM11_STOP=B_0x0, DBG_I2C1_STOP=B_0x0, DBG_TIM4_STOP=B_0x0, DBG_TIM7_STOP=B_0x0, DBG_TIM2_STOP=B_0x0, DBG_I2C2_STOP=B_0x0, DBG_I3C1_STOP=B_0x0, DBG_TIM6_STOP=B_0x0, DBG_TIM10_STOP=B_0x0, DBG_LPTIM1_STOP=B_0x0

Description

DBGMCU APB1L peripheral freeze register

Fields

DBG_TIM2_STOP

TIM2 stop in debug

0 (B_0x0): Normal operation. TIM2 continues to operate while Cortex-M55 is in debug mode.

1 (B_0x1): Stop in debug. TIM2 is frozen while Cortex-M55 is in debug mode.
DBG_TIM3_STOP

TIM3 stop in debug

0 (B_0x0): Normal operation. TIM3 continues to operate while Cortex-M55 is in debug mode.

1 (B_0x1): Stop in debug. TIM3 is frozen while Cortex-M55 is in debug mode.
DBG_TIM4_STOP

TIM4 stop in debug

0 (B_0x0): Normal operation. TIM4 continues to operate while Cortex-M55 is in debug mode.

1 (B_0x1): Stop in debug. TIM4 is frozen while Cortex-M55 is in debug mode.
DBG_TIM5_STOP

TIM5 stop in debug

0 (B_0x0): Normal operation. TIM5 continues to operate while Cortex-M55 is in debug mod.e

1 (B_0x1): Stop in debug. TIM5 is frozen while Cortex-M55 is in debug mode.
DBG_TIM6_STOP

TIM6 stop in debug

0 (B_0x0): Normal operation. TIM6 continues to operate while Cortex-M55 is in debug mode.

1 (B_0x1): Stop in debug. TIM6 is frozen while Cortex-M55 is in debug mode.
DBG_TIM7_STOP

TIM7 stop in debug

0 (B_0x0): Normal operation. TIM7 continues to operate while Cortex-M55 is in debug mode.

1 (B_0x1): Stop in debug. TIM7 is frozen while Cortex-M55 is in debug mode.
DBG_TIM12_STOP

TIM12 stop in debug

0 (B_0x0): Normal operation. TIM12 continues to operate while Cortex-M55 is in debug mode.

1 (B_0x1): Stop in debug. TIM12 is frozen while Cortex-M55 is in debug mode.
DBG_TIM13_STOP

TIM13 stop in debug

0 (B_0x0): Normal operation. TIM13 continues to operate while Cortex-M55 is in debug mode.

1 (B_0x1): Stop in debug. TIM13 is frozen while Cortex-M55 is in debug mode.
DBG_TIM14_STOP

TIM14 stop in debug

0 (B_0x0): Normal operation. TIM14 continues to operate while Cortex-M55 is in debug mode.

1 (B_0x1): Stop in debug. TIM14 is frozen while Cortex-M55 is in debug mode.
DBG_LPTIM1_STOP

LPTIM1 stop in debug

0 (B_0x0): Normal operation. LPTIM1 continues to operate while Cortex-M55 is in debug mode.

1 (B_0x1): Stop in debug. LPTIM1 is frozen while Cortex-M55 is in debug mode.
DBG_WWDG1_STOP

WWDG1 stop in debug

0 (B_0x0): Normal operation. WWDG1 continues to operate while Cortex-M55 is in debug mode.

1 (B_0x1): Stop in debug. WWDG1 is frozen while Cortex-M55 is in debug mode.
DBG_TIM10_STOP

TIM10 stop in debug

0 (B_0x0): Normal operation. TIM10 continues to operate while Cortex-M55 is in debug mode.

1 (B_0x1): Stop in debug. TIM10 is frozen while Cortex-M55 is in debug mode.
DBG_TIM11_STOP

TIM11 stop in debug

0 (B_0x0): Normal operation. TIM11 continues to operate while Cortex-M55 is in debug mode.

1 (B_0x1): Stop in debug. TIM11 is frozen while Cortex-M55 is in debug mode.
DBG_I2C1_STOP

I2C1 SMBUS timeout stop in debug

0 (B_0x0): Normal operation. I2C1 SMBUS timeout continues to operate while Cortex-M55 is in debug mode.

1 (B_0x1): Stop in debug. I2C1 SMBUS timeout is frozen while Cortex-M55 is in debug mode.
DBG_I2C2_STOP

I2C2 SMBUS timeout stop in debug

0 (B_0x0): Normal operation. I2C2 SMBUS timeout continues to operate while Cortex-M55 is in debug mode.

1 (B_0x1): Stop in debug. I2C2 SMBUS timeout is frozen while Cortex-M55 is in debug mode.
DBG_I2C3_STOP

I2C3 SMBUS timeout stop in debug

0 (B_0x0): Normal operation. I2C3 SMBUS timeout continues to operate while Cortex-M55 is in debug mode.

1 (B_0x1): Stop in debug. I2C3 SMBUS timeout is frozen while Cortex-M55 is in debug mode.
DBG_I3C1_STOP

I3C1 SMBUS timeout stop in debug

0 (B_0x0): Normal operation. I3C1 SMBUS timeout continues to operate while Cortex-M55 is in debug mode.

1 (B_0x1): Stop in debug. I3C1 SMBUS timeout is frozen while Cortex-M55 is in debug mode.
DBG_I3C2_STOP

I3C2 SMBUS timeout stop in debug

0 (B_0x0): Normal operation. I3C2 SMBUS timeout continues to operate while Cortex-M55 is in debug mode.

1 (B_0x1): Stop in debug. I3C2 SMBUS timeout is frozen while Cortex-M55 is in debug mode.

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32