VSPOL=B_0x0, ESS=B_0x0, ENABLE=B_0x0, SWAPBITS=B_0x0, PCKPOL=B_0x0, EDM=B_0x0, HSPOL=B_0x0, SWAPCYCLES=B_0x0
DCMIPP parallel interface control register
| ESS | Embedded synchronization select 0 (B_0x0): Hardware synchronization data capture (frame/line start/stop) is synchronized with the HSYNC/VSYNC signals. 1 (B_0x1): Embedded synchronization data capture is synchronized with synchronization codes embedded in the data flow. |
| PCKPOL | Pixel clock polarity 0 (B_0x0): Falling edge active 1 (B_0x1): Rising edge active |
| HSPOL | Horizontal synchronization polarity 0 (B_0x0): HSYNC active low 1 (B_0x1): HSYNC active high |
| VSPOL | Vertical synchronization polarity 0 (B_0x0): VSYNC active low 1 (B_0x1): VSYNC active high |
| EDM | Extended data mode 0 (B_0x0): Interface captures 8-bit data on every pixel clock 1 (B_0x1): Interface captures 10-bit data on every pixel clock 2 (B_0x2): Interface captures 12-bit data on every pixel clock 3 (B_0x3): Interface captures 14-bit data on every pixel clock 4 (B_0x4): Interface captures 16-bit data on every pixel clock |
| ENABLE | Parallel interface enable 0 (B_0x0): Parallel interface disabled to lower power consumption 1 (B_0x1): Parallel interface enabled |
| FORMAT | Other values: data are captured and output as-is only through the data/dump pipeline (e.g. JPEG or byte input format). 30 (B_0x1E): YUV422 34 (B_0x22): RGB565 36 (B_0x24): RGB888 (= YUV444) 42 (B_0x2A): RAW8 43 (B_0x2B): RAW10 44 (B_0x2C): RAW12 45 (B_0x2D): RAW14 74 (B_0x4A): monochrome 8-bit 75 (B_0x4B): monochrome 10-bit 76 (B_0x4C): monochrome 12-bit 77 (B_0x4D): monochrome 14-bit 90 (B_0x5A): byte stream (JPEG, compressed video) |
| SWAPCYCLES | Swap data (cycle 0 vs. cycle 1) for pixels received on two cycles 0 (B_0x0): Default 1 (B_0x1): Swap active: the data of cycle 1 is used before the data of cycle 0. |
| SWAPBITS | Swap LSB vs. MSB within each received component 0 (B_0x0): As received 1 (B_0x1): Swapped MSB vs. LSB |