Regviz

stm32 /stm32n6 /STM32N647 /DTS /DTS_TS0HLSAMPLER

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Interpret as DTS_TS0HLSAMPLER

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SMPL_LO0SMPL_HI

Description

DTS TS0 high/low sample register

Fields

SMPL_LO

Lowest valid data sample value received
SMPL_HI

Highest valid data sample value received

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32