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stm32 /stm32n6 /STM32N647 /DTS /DTS_TSCSMPL_CR

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Interpret as DTS_TSCSMPL_CR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)SMPL_CTR_DISABLE 0 (B_0x0)SMPL_CTR_HOLD 0 (B_0x0)SMPL_DISCARD

SMPL_CTR_HOLD=B_0x0, SMPL_CTR_DISABLE=B_0x0, SMPL_DISCARD=B_0x0

Description

DTS TSC sample control register

Fields

SMPL_CTR_DISABLE

Sample counter disable bit

0 (B_0x0): Sample counter enabled

1 (B_0x1): Sample counter disabled
SMPL_CTR_HOLD

Sample counter hold bit

0 (B_0x0): Counter not on hold

1 (B_0x1): Counter on hold
SMPL_DISCARD

Sample discard bit

0 (B_0x0): Data samples not discarded

1 (B_0x1): Data samples discarded

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32