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stm32 /stm32n6 /STM32N647 /ETH /ETH_DMAC1TXCR

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Interpret as ETH_DMAC1TXCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ST)ST 0TCW0 (OSF)OSF 0 (TSE)TSE 0 (IPBL)IPBL 0TXPBL0TQOS0 (EDSE)EDSE

Description

Channel 1 transmit control register

Fields

ST

Start or Stop Transmission Command
TCW

Transmit Channel Weight
OSF

Operate on Second Packet
TSE

TCP Segmentation Enabled
IPBL

Ignore PBL Requirement
TXPBL

Transmit Programmable Burst Length
TQOS

Transmit QOS
EDSE

Enhanced Descriptor Enable

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32