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stm32 /stm32n6 /STM32N647 /ETH /ETH_DMAC1TXRLR

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Interpret as ETH_DMAC1TXRLR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TDRL

Description

Channel 1 T1 descriptor ring length register

Fields

TDRL

Transmit Descriptor Ring Length

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32