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stm32 /stm32n6 /STM32N647 /ETH /ETH_DMAISR

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Interpret as ETH_DMAISR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DC0IS)DC0IS 0 (DC1IS)DC1IS 0 (MTLIS)MTLIS 0 (MACIS)MACIS

Description

Interrupt status register

Fields

DC0IS

DMA Channel 0 Interrupt Status
DC1IS

DMA Channel 1 Interrupt Status
MTLIS

MTL Interrupt Status
MACIS

MAC Interrupt Status

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32