stm32 /stm32n6 /STM32N647 /ETH /ETH_DMAMR

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Interpret as ETH_DMAMR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SWR)SWR 0 (B_0x0)TAA0 (B_0x0)DSPW 0 (TXPR)TXPR 0INTM

TAA=B_0x0, DSPW=B_0x0

Description

DMA mode register

Fields

SWR

Software Reset

TAA

Transmit Arbitration Algorithm

0 (B_0x0): Fixed priority. In fixed priority, Channel 0 has the lowest priority and the last channel has the highest priority.

1 (B_0x1): Weighted Strict priority (WSP)

2 (B_0x2): Weighted Round-Robin (WRR)

DSPW

Descriptor Posted Write

0 (B_0x0): The descriptor writes are always non-posted.

1 (B_0x1): The descriptor writes are non-posted only when IOC (Interrupt on completion) is set in last descriptor. Otherwise, the descriptor writes are always posted.

TXPR

Transmit priority

INTM

Interrupt Mode

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