stm32 /stm32n6 /STM32N647 /ETH /ETH_MACHWF2R

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Interpret as ETH_MACHWF2R

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)RXQCNT0 (B_0x0)TXQCNT0 (B_0x0)RXCHCNT0 (B_0x0)RDCSZ 0 (B_0x0)TXCHCNT0 (B_0x0)TDCSZ 0 (B_0x0)PPSOUTNUM 0 (B_0x0)AUXSNAPNUM

TXCHCNT=B_0x0, TXQCNT=B_0x0, RXCHCNT=B_0x0, RXQCNT=B_0x0, TDCSZ=B_0x0, AUXSNAPNUM=B_0x0, PPSOUTNUM=B_0x0, RDCSZ=B_0x0

Description

HW feature 2 register

Fields

RXQCNT

Number of MTL Receive Queues

0 (B_0x0): 1 MTL Rx queue

1 (B_0x1): 2 MTL Rx queues

7 (B_0x7): 8 MTL Rx

TXQCNT

Number of MTL Transmit Queues

0 (B_0x0): 1 MTL Tx queue

1 (B_0x1): 2 MTL Tx queues

7 (B_0x7): 8 MTL Tx

RXCHCNT

Number of DMA Receive Channels

0 (B_0x0): 1 DMA Rx Channel

1 (B_0x1): 2 DMA Rx Channels

7 (B_0x7): 8 DMA Rx

RDCSZ

Rx DMA Descriptor Cache Size in terms of 16-byte descriptors

0 (B_0x0): Cache not configured

1 (B_0x1): Four 16-byte descriptors

2 (B_0x2): Eight 16-byte descriptors

3 (B_0x3): Sixteen 16-byte descriptors

TXCHCNT

Number of DMA Transmit Channels

0 (B_0x0): 1 DMA Tx Channel

1 (B_0x1): 2 DMA Tx Channels

7 (B_0x7): 8 DMA Tx

TDCSZ

Tx DMA Descriptor Cache Size in terms of 16-byte descriptors

0 (B_0x0): Cache not configured

1 (B_0x1): Four 16-byte descriptors

2 (B_0x2): Eight 16-byte descriptors

3 (B_0x3): Sixteen 16-byte descriptors

PPSOUTNUM

Number of PPS Outputs

0 (B_0x0): No PPS output

1 (B_0x1): 1 PPS output

2 (B_0x2): 2 PPS outputs

3 (B_0x3): 3 PPS outputs

4 (B_0x4): 4 PPS outputs

AUXSNAPNUM

Number of Auxiliary Snapshot Inputs

0 (B_0x0): No auxiliary input

1 (B_0x1): 1 auxiliary input

2 (B_0x2): 2 auxiliary inputs

3 (B_0x3): 3 auxiliary inputs

4 (B_0x4): 4 auxiliary inputs

Links

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