stm32 /stm32n6 /STM32N647 /ETH /ETH_MACHWF3R

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Interpret as ETH_MACHWF3R

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)NRVF0 (CBTISEL)CBTISEL 0 (DVLAN)DVLAN 0 (PDUPSEL)PDUPSEL 0 (FRPSEL)FRPSEL 0 (B_0x0)FRPBS 0 (B_0x0)FRPES 0 (ESTSEL)ESTSEL 0 (B_0x0)ESTDEP 0 (B_0x0)ESTWID 0 (FPESEL)FPESEL 0 (TBSSEL)TBSSEL 0 (B_0x0)ASP

FRPES=B_0x0, ESTWID=B_0x0, ESTDEP=B_0x0, FRPBS=B_0x0, ASP=B_0x0, NRVF=B_0x0

Description

HW feature 3 register

Fields

NRVF

Number of Extended VLAN Tag Filters Enabled

0 (B_0x0): No Extended Rx VLAN Filters

1 (B_0x1): 4 Extended Rx VLAN Filters

2 (B_0x2): 8 Extended Rx VLAN Filters

3 (B_0x3): 16 Extended Rx VLAN Filters

4 (B_0x4): 24 Extended Rx VLAN Filters

5 (B_0x5): 32 Extended Rx VLAN Filters

CBTISEL

Queue/Channel based VLAN tag insertion on Tx enable

DVLAN

Double VLAN processing enable

PDUPSEL

Broadcast/Multicast Packet Duplication

FRPSEL

Flexible Receive Parser Selected

FRPBS

Flexible Receive Parser Buffer size

0 (B_0x0): 64 bytes

1 (B_0x1): 128 bytes

2 (B_0x2): 256 bytes

FRPES

Flexible Receive Parser Table Entries size

0 (B_0x0): 64 entries

1 (B_0x1): 128 entries

2 (B_0x2): 256 entries

ESTSEL

Enhancements to Scheduled Traffic Enable

ESTDEP

Depth of the Gate Control List

0 (B_0x0): No depth

1 (B_0x1): 64

2 (B_0x2): 128

3 (B_0x3): 256

4 (B_0x4): 512

5 (B_0x5): 1024

ESTWID

Width of the Time Interval field in the Gate Control List

0 (B_0x0): No width

1 (B_0x1): 16

2 (B_0x2): 20

3 (B_0x3): 24

FPESEL

Frame Preemption Enable

TBSSEL

Time-based scheduling Enable

ASP

Automotive Safety Package

0 (B_0x0): None

1 (B_0x1): ECC only

2 (B_0x2): AS_NPPE

3 (B_0x3): AS_PPE

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