DMCHN0=B_0x0, L3HSBM0=B_0x0_IPV4_PACKETS, L3HDBM0=B_0x0_IPV4_PACKETS
L3 and L4 control 0 register
| L3PEN0 | Layer 3 Protocol Enable |
| L3SAM0 | Layer 3 IP SA Match Enable |
| L3SAIM0 | Layer 3 IP SA Inverse Match Enable |
| L3DAM0 | Layer 3 IP DA Match Enable |
| L3DAIM0 | Layer 3 IP DA Inverse Match Enable |
| L3HSBM0 | Layer 3 IP SA higher bits match 0 (B_0x0_IPV4_PACKETS): No bits are masked. 1 (B_0x1_IPV4_PACKETS): LSb[0] is masked |
| L3HDBM0 | Layer 3 IP DA higher bits match 0 (B_0x0_IPV4_PACKETS): No bits are masked. 1 (B_0x1_IPV4_PACKETS): LSb[0] is masked |
| L4PEN0 | Layer 4 Protocol Enable |
| L4SPM0 | Layer 4 Source Port Match Enable |
| L4SPIM0 | Layer 4 Source Port Inverse Match Enable |
| L4DPM0 | Layer 4 Destination Port Match Enable |
| L4DPIM0 | Layer 4 Destination Port Inverse Match Enable |
| DMCHN0 | DMA Channel Number 0 (B_0x0): DMA channel 0 1 (B_0x1): DMA channel 1 |
| DMCHEN0 | DMA Channel Select Enable |