L3HDBM1=B_0x0_IPV4_PACKETS, L3HSBM1=B_0x0_IPV4_PACKETS
L3 and L4 control 1 register
| L3PEN1 | Layer 3 Protocol Enable |
| L3SAM1 | Layer 3 IP SA Match Enable |
| L3SAIM1 | Layer 3 IP SA Inverse Match Enable |
| L3DAM1 | Layer 3 IP DA Match Enable |
| L3DAIM1 | Layer 3 IP DA Inverse Match Enable |
| L3HSBM1 | Layer 3 IP SA Higher Bits Match 0 (B_0x0_IPV4_PACKETS): No bits are masked. 1 (B_0x1_IPV4_PACKETS): LSb[0] is masked |
| L3HDBM1 | Layer 3 IP DA higher bits match 0 (B_0x0_IPV4_PACKETS): No bits are masked. 1 (B_0x1_IPV4_PACKETS): LSb[0] is masked |
| L4PEN1 | Layer 4 Protocol Enable |
| L4SPM1 | Layer 4 Source Port Match Enable |
| L4SPIM1 | Layer 4 Source Port Inverse Match Enable |
| L4DPM1 | Layer 4 Destination Port Match Enable |
| L4DPIM1 | Layer 4 Destination Port Inverse Match Enable |
| DMCHN1 | DMA Channel Number |
| DMCHEN1 | DMA Channel Select Enable |