CR=B_0x0
MDIO address register
| GB | GMII Busy |
| C45E | Clause 45 PHY Enable |
| GOC | GMII Operation Command 1 (B_0x1): Write 2 (B_0x2): Post Read Increment Address for Clause 45 PHY 3 (B_0x3): Read |
| SKAP | Skip Address Packet |
| CR | CSR Clock Range 0 (B_0x0): CSR clock = 60-100 MHz; MDC clock = CSR clock/42 1 (B_0x1): CSR clock = 100-150 MHz; MDC clock = CSR clock/62 2 (B_0x2): CSR clock = 20-35 MHz; MDC clock = CSR clock/16 3 (B_0x3): CSR clock = 35-60 MHz; MDC clock = CSR clock/26 4 (B_0x4): CSR clock = 150-250 MHz; MDC clock = CSR clock/102 5 (B_0x5): CSR clock = 250-300 MHz; MDC clock = CSR clock/124 6 (B_0x6): CSR clock = 300-500 MHz; MDC clock = CSR clock/204 7 (B_0x7): CSR clock = 500-800 MHz; MDC clock = CSR clock/324 8 (B_0x8): CSR clock/4 9 (B_0x9): CSR clock/6 10 (B_0xA): CSR clock/8 11 (B_0xB): CSR clock/10 12 (B_0xC): CSR clock/12 13 (B_0xD): CSR clock/14 14 (B_0xE): CSR clock/16 15 (B_0xF): CSR clock/18 |
| NTC | Number of Training Clocks |
| RDA | Register/Device Address |
| PA | Physical Layer Address |
| BTB | Back to Back transactions |
| PSE | Preamble Suppression Enable |