Regviz

stm32 /stm32n6 /STM32N647 /ETH /ETH_MMC_RX_INTERRUPT_MASK

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as ETH_MMC_RX_INTERRUPT_MASK

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32n6/STM32N645/ETH/ETH_MMC_RX_INTERRUPT_MASK#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RXCRCERPIM)RXCRCERPIM 0 (RXALGNERPIM)RXALGNERPIM 0 (RXUCGPIM)RXUCGPIM 0 (RXLPIUSCIM)RXLPIUSCIM 0 (RXLPITRCIM)RXLPITRCIM

Description

MMC Rx interrupt mask register

Fields

RXCRCERPIM

MMC Receive CRC Error Packet Counter Interrupt Mask
RXALGNERPIM

MMC Receive Alignment Error Packet Counter Interrupt Mask
RXUCGPIM

MMC Receive Unicast Good Packet Counter Interrupt Mask
RXLPIUSCIM

MMC Receive LPI microsecond counter interrupt Mask
RXLPITRCIM

MMC Receive LPI transition counter interrupt Mask

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32