stm32 /stm32n6 /STM32N647 /ETH /ETH_MTLESTGCLCR

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Interpret as ETH_MTLESTGCLCR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SRWO)SRWO 0 (B_0x0)R1W0 0 (GCRR)GCRR 0 (DBGM)DBGM 0 (B_0x0)DBGB 0 (B_0x0_GCRR__EQUAL_1)ADDR

R1W0=B_0x0, DBGB=B_0x0, ADDR=B_0x0_GCRR__EQUAL_1

Description

EST Gate Control List Register

Fields

SRWO

Start Read/Write Operation

1 (B_0x1): Indicates the start/progress of a Read/Write operation

R1W0

Read 1, Write 0

0 (B_0x0): Write operation.

1 (B_0x1): Read operation

GCRR

Gate Control Related Registers

DBGM

Debug Mode

DBGB

Debug Mode Bank Select

0 (B_0x0): Bank 0

1 (B_0x1): Bank 1

ADDR

Gate Control List Address:

0 (B_0x0_GCRR__EQUAL_1): BTR Low (31:0)

1 (B_0x1_GCRR__EQUAL_1): BTR High (63:31)

2 (B_0x2_GCRR__EQUAL_1): CTR Low (31:0)

3 (B_0x3_GCRR__EQUAL_1): CTR High (39:32)

4 (B_0x4_GCRR__EQUAL_1): TER (30:0)

5 (B_0x5_GCRR__EQUAL_1): LLR (6:0)

Links

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