Regviz

stm32 /stm32n6 /STM32N647 /ETH /ETH_MTLESTSR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as ETH_MTLESTSR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32n6/STM32N645/ETH/ETH_MTLESTSR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)SWLC 0 (B_0x0)BTRE 0 (HLBF)HLBF 0 (B_0x0)HLBS 0 (B_0x0)CGCE 0 (B_0x0)SWOL 0BTRL0CGSN

SWOL=B_0x0, HLBS=B_0x0, CGCE=B_0x0, BTRE=B_0x0, SWLC=B_0x0

Description

EST Status Register

Fields

SWLC

Switch to S/W owned list Complete

0 (B_0x0): Inactive

1 (B_0x1): Active
BTRE

BTR Error

0 (B_0x0): Inactive

1 (B_0x1): Active
HLBF

Head-Of-Line Blocking due to Frame Size
HLBS

Head-Of-Line Blocking due to Scheduling

0 (B_0x0): Inactive

1 (B_0x1): Active
CGCE

Constant Gate Control Error

0 (B_0x0): Inactive

1 (B_0x1): Active
SWOL

S/W owned list

0 (B_0x0): Inactive

1 (B_0x1): Active
BTRL

BTR Error Loop Count
CGSN

Current GCL slot number

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32