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stm32 /stm32n6 /STM32N647 /ETH /ETH_MTLQ0ICSR

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Interpret as ETH_MTLQ0ICSR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TXUNFIS)TXUNFIS 0 (ABPSIS)ABPSIS 0 (TXUIE)TXUIE 0 (ABPSIE)ABPSIE 0 (RXOVFIS)RXOVFIS 0 (RXOIE)RXOIE

Description

Queue 0 interrupt control status Register

Fields

TXUNFIS

Transmit Queue Underflow Interrupt Status
ABPSIS

Average Bits Per Slot Interrupt Status
TXUIE

Transmit Queue Underflow Interrupt Enable
ABPSIE

Average Bits Per Slot Interrupt Enable
RXOVFIS

Receive Queue Overflow Interrupt Status
RXOIE

Receive Queue Overflow Interrupt Enable

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32