Regviz

stm32 /stm32n6 /STM32N647 /ETH /ETH_MTLTXQ0UR

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Interpret as ETH_MTLTXQ0UR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0UFFRMCNT0 (UFCNTOVF)UFCNTOVF

Description

T0 queue 0 underflow register

Fields

UFFRMCNT

Underflow Packet Counter
UFCNTOVF

Overflow Bit for Underflow Packet Counter

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32