stm32 /stm32n6 /STM32N647 /ETH /ETH_MTLTXQ1DR

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Interpret as ETH_MTLTXQ1DR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TXQPAUSED)TXQPAUSED 0 (B_0x0)TRCSTS 0 (TWCSTS)TWCSTS 0 (TXQSTS)TXQSTS 0 (TXSTSFSTS)TXSTSFSTS 0PTXQ0STXSTSF

TRCSTS=B_0x0

Description

T1 queue 1 debug register

Fields

TXQPAUSED

Transmit Queue in Pause

TRCSTS

MTL Tx Queue Read Controller Status

0 (B_0x0): Idle state

1 (B_0x1): Read state (transferring data to the MAC transmitter)

2 (B_0x2): Waiting for pending Tx Status from the MAC transmitter

3 (B_0x3): Flushing the Tx queue because of the Packet Abort request from the MAC

TWCSTS

MTL Tx Queue Write Controller Status

TXQSTS

MTL Tx Queue Not Empty Status

TXSTSFSTS

MTL Tx Status FIFO Full Status

PTXQ

Number of Packets in the Transmit Queue

STXSTSF

Number of Status Words in Tx Status FIFO of Queue

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