RF1L=B_0x0, F1F=B_0x0, DMS=B_0x0
FDCAN Rx FIFO 1 status register
| F1FL | Rx FIFO 1 fill level |
| F1GI | Rx FIFO 1 get index |
| F1PI | Rx FIFO 1 put index |
| F1F | Rx FIFO 1 full 0 (B_0x0): Rx FIFO 1 not full 1 (B_0x1): Rx FIFO 1 full |
| RF1L | Rx FIFO 1 message lost 0 (B_0x0): No Rx FIFO 1 message lost 1 (B_0x1): Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size 0. |
| DMS | Debug message status 0 (B_0x0): Idle state, wait for reception of debug messages 1 (B_0x1): Debug message A received 2 (B_0x2): Debug messages A, B received 3 (B_0x3): Debug messages A, B, C received |