DATAHLD=B_0x0, ADDSET=B_0x0, DATLAT=B_0x0, CLKDIV=B_0x0, BUSTURN=B_0x0, ACCMOD=B_0x0
SRAM/NOR Flash chip-select timing registers for memory region 2
| ADDSET | Address setup phase duration 0 (B_0x0): ADDSET phase duration = 0 * fmc_ker_ck clock cycle 15 (B_0xF): ADDSET phase duration = 15 * fmc_ker_ck clock cycles (default value after reset) |
| ADDHLD | Address-hold phase duration 1 (B_0x1): ADDHLD phase duration =1 * fmc_ker_ck clock cycle 2 (B_0x2): ADDHLD phase duration = 2 * fmc_ker_ck clock cycle 15 (B_0xF): ADDHLD phase duration = 15 * fmc_ker_ck clock cycles (default value after reset) |
| DATAST | Data-phase duration 1 (B_0x1): DATAST phase duration = 1 * fmc_ker_ck clock cycles 2 (B_0x2): DATAST phase duration = 2 * fmc_ker_ck clock cycles 255 (B_0xFF): DATAST phase duration = 255 * fmc_ker_ck clock cycles (default value after reset) |
| BUSTURN | Bus turnaround phase duration 0 (B_0x0): BUSTURN phase duration = 1 * fmc_ker_ck clock cycle added 15 (B_0xF): BUSTURN phase duration = 16 * fmc_ker_ck clock cycles added (default value after reset) |
| CLKDIV | Clock divide ratio (for FMC_CLK signal) 0 (B_0x0): FMC_CLK period= 1x fmc_ker_ck period 1 (B_0x1): FMC_CLK period = 2 fmc_ker_ck periods 2 (B_0x2): FMC_CLK period = 3 fmc_ker_ck periods 15 (B_0xF): FMC_CLK period = 16 fmc_ker_ck periods (default value after reset) |
| DATLAT | Data latency for synchronous memory (see note below bit descriptions) 0 (B_0x0): Data latency of 2 FMC_CLK clock cycles for first burst access 15 (B_0xF): Data latency of 17 FMC_CLK clock cycles for first burst access (default value after reset) |
| ACCMOD | Access mode 0 (B_0x0): Access mode A 1 (B_0x1): Access mode B 2 (B_0x2): Access mode C 3 (B_0x3): Access mode D |
| DATAHLD | Data Hold phase duration 0 (B_0x0): DATAHLD phase duration = fmc_ker_ck clock cycle * 0 (default, read)/1 (default, write) 1 (B_0x1): DATAHLD phase duration = fmc_ker_ck clock cycle * 1 (read)/2 (write) 2 (B_0x2): DATAHLD phase duration = fmc_ker_ck clock cycle * 2 (read)/3 (write) 3 (B_0x3): DATAHLD phase duration = fmc_ker_ck clock cycle * 3 (read)/4 (write) |