stm32 /stm32n6 /STM32N647 /GPDMA /GPDMA_C9LLR

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Interpret as GPDMA_C9LLR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0LA0 (B_0x0)ULL 0 (B_0x0)UDA 0 (B_0x0)USA 0 (B_0x0)UB1 0 (B_0x0)UT2 0 (B_0x0)UT1

ULL=B_0x0, UB1=B_0x0, USA=B_0x0, UT2=B_0x0, UDA=B_0x0, UT1=B_0x0

Description

GPDMA channel 9 linked-list address register

Fields

LA

pointer (16-bit low-significant address) to the next linked-list data structure

ULL

Update GPDMA_CxLLR register from memory

0 (B_0x0): no GPDMA_CxLLR update

1 (B_0x1): GPDMA_CxLLR update

UDA

Update GPDMA_CxDAR register from memory

0 (B_0x0): no GPDMA_CxDAR update

1 (B_0x1): GPDMA_CxDAR update

USA

update GPDMA_CxSAR from memory

0 (B_0x0): no GPDMA_CxSAR update

1 (B_0x1): GPDMA_CxSAR update

UB1

Update GPDMA_CxBR1 from memory

0 (B_0x0): no GPDMA_CxBR1 update from memory (GPDMA_CxBR1.BNDT[15:0] restored if any link transfer)

1 (B_0x1): GPDMA_CxBR1 update

UT2

Update GPDMA_CxTR2 from memory

0 (B_0x0): no GPDMA_CxTR2 update

1 (B_0x1): GPDMA_CxTR2 update

UT1

Update GPDMA_CxTR1 from memory

0 (B_0x0): no GPDMA_CxTR1 update

1 (B_0x1): GPDMA_CxTR1 update

Links

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