stm32 /stm32n6 /STM32N647 /HPDMA /HPDMA_C11SEMCR

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Interpret as HPDMA_C11SEMCR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0_WRITE)SEM_MUTEX 0 (B_0x0)SEM_CCID

SEM_MUTEX=B_0x0_WRITE, SEM_CCID=B_0x0

Description

HPDMA channel 11 semaphore control register

Fields

SEM_MUTEX

mutual exclusion semaphore for the CID allocation of the channel x (in semaphore mode)

0 (B_0x0_WRITE): release the control of the channel x (in semaphore mode) to any white-listed CID

1 (B_0x1_WRITE): take the control of the channel x (in semaphore mode), from one of the white-listed CID pool

SEM_CCID

current CID allocated to the channel x (in semaphore mode)

0 (B_0x0): CID0 is the last white-listed CID that took the control of the channel x.

1 (B_0x1): CID1 is the last white-listed CID that took the control of the channel x.

2 (B_0x2): CID2 is the last white-listed CID that took the control of the channel x.

3 (B_0x3): CID3 is the last white-listed CID that took the control of the channel x.

4 (B_0x4): CID4 is the last white-listed CID that took the control of the channel x.

5 (B_0x5): CID5 is the last white-listed CID that took the control of the channel x.

6 (B_0x6): CID6 is the last white-listed CID that took the control of the channel x.

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